[1] Sonka M, Václav Hlavác, Boyle R. Image Processing, Analysis and Machine Vision[M]. New York: Cengage Learning, 2014.
[2] Ishikawa M, Ogawa K, Komuro T, et al. A CMOS vision chip with SIMD processing element array for 1 ms image processing[C]//IEEE Int Solid-State Circuits Conf, 1999: 206-207.
[3] Miao W, Lin Q, Zhang W, et al. A programmable SIMD vision chip for real-time vision applications [J]. IEEE Journal of Solid-State Circuits, 2008, 43(6): 1470−1479. doi:  10.1109/JSSC.2008.923621
[4] Zhang W, Fu Q, Wu N. A programmable vision chip based on multiple levels of parallel processors [J]. IEEE Journal of Solid-State Circuits, 2011, 46(9): 2132−2147. doi:  10.1109/JSSC.2011.2158024
[5] Shi C, Yang J, Han Y, et al. A 1000 fps vision chip based on a dynamically reconfigurable hybrid architecture comprising a PE array and self-organizing map neural network[C]//2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014: 128-129.
[6] Yamazaki T, Katayama H, Uehara S, et al. 4.9 A 1 ms high-speed vision chip with 3D-stacked 140GOPS column-parallel PEs for spatio-temporal image processing[C]//2017 IEEE International Solid- State Circuits Conference (ISSCC), 2017: 82-83.
[7] Yang J, Yang Y, Chen Z, et al. A heterogeneous parallel processor for high-speed vision chip [J]. IEEE Transactions on Circuits and Systems for Video Technology, 2018, 28(3): 746−758. doi:  10.1109/TCSVT.2016.2618753
[8] Krizhevsky A, Sutskever I, Hinton G E. Imagenet classification with deep convolutional neural networks[C]//Advances in Neural Information Processing Systems. 2012: 1097-1105.
[9] Sze V, Chen Y, Yang T, et al. Efficient processing of deep neural networks: A tutorial and survey [J]. Proceedings of the IEEE, 2017, 105(12): 2295−2329. doi:  10.1109/JPROC.2017.2761740
[10] Chen T, Du Z, Sun N, et al. Diannao: A small-footprint high-throughput accelerator for ubiquitous machine-learning [J]. ACM Sigplan Notices, 2014, 49(4): 269−284.
[11] Liu D, Chen T, Liu S, et al. Pudiannao: A polyvalent machine learning accelerator[C]//ACM SIGARCH Computer Architecture News. ACM, 2015, 43(1): 369-381.
[12] Millet L, Chevobbe S, Andriamisaina C, et al. A 5500FPS 85GOPS/W 3D stacked BSI vision chip based on parallel in-focal-plane acquisition and processing[C]//2018 IEEE Symposium on VLSI Circuits. IEEE, 2018: 245-246.
[13] Chen Y, Krishna T, Emer J, et al. 14.5 Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks[C]//2016 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, 2016: 262-263.
[14] Jo J, Cha S, Rho D, et al. DSIP: A scalable inference accelerator for convolutional neural networks [J]. IEEE Journal of Solid-State Circuits, 2017, 53(2): 605−618.