Abstract: HgCdTe electron injection avalanche photodiodes(e-APDs) work in linear mode. A weak optical current signal is amplified orders of magnitude due to the internal avalanche mechanism. The design of digital ROIC with a column-shared ADC for cooled (77 K) hybrid e-APDs FPA was presented in this paper. Sigma-delta conversion was a promising solution for high-performance and medium size FPA as 128 128. A multistage noise shaping (MASH) 2 -1 single bit architecture sigma-delta ADC with switched-capacitor circuits was designed for column-shared ADC. A cascaded integrator-comb (CIC) filter was designed as the digital decimator filter. The circuit was implemented in the GLOBALFOUNDRIES 0.35 m CMOS process on the basis of a 100 m pixel pitch. A quantization noise subtraction circuit in modulator was designed to subtract the quantization noise of first-stage modulator. The register word length of the filter in each stage was carefully dimensioned in order to minimize the required hardware. Furthermore, the digital filters operate with a reduced supply voltage to 1.5 V. Simulation results showed that the sigma-delta conversion achieved the resolution higher than 13 bits and 2.4 mW power consumption per ADC at 7.7 k Samples/s rate.