Abstract: The internal structure and work patterns of the surface array CCD485, were described and the basic drive circuit design was given. And then through the array CCD485 drive timing diagram analysis, based on the timing segments and the general purpose of the finite state machinetype full frame area array CCD drive timing generator, the grouping method by the CCD drive timing, the timing waveforms of each group was divided into a number of basic output state, so that the drive timing of the CCD for each session canby combination of the basic state, and Moore finite state machine to describe the timing-driven modular design. The specific design of each module was given, the timing generator of the design process easier, and finally using Xilinx Virtex-Ⅱ Pro series FPGA-XC2VP20 and Xilinx's ISE software platform, CCD drive timing generator was designed, and simulation waveform analysis was completed. The output meet the timing requirements of 485-chip driver, the effectiveness of the design method is proven.