SRAM-based FPGA SEU simulation system

SRAM-based FPGA in the space radiation environment is effected by single event, which leads to the occurrence of FPGA memory cell bit flip. When the flip up to a certain extent, the function may become errors. To assess the sensitivity of FPGA single event and improve the reliability of FPGA single event, the key technology to realize fault injection was studied, the existing technology was analyzed, SEU sensitive bit test system was designed, based on partial reconfiguration feature of SRAM-based FPGA, and the modified FPGA configuration data bits was used to simulate a fault zone, the method accelerated the process of system failure, realized the single event upset sensitive position detection and statistics. Experiments show that the design is reasonable, implementation is flexibale, and cost is low, and provides favorable support for SRAM-based FPGA anti-tolerant design.