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典型的基于光子飞行时间(Time of Flight, TOF)的成像系统架构如图4所示。系统工作时,首先由主机/延时器(Host/Delayer)发出系统启动指令,ROIC完成测量前的电路复位,系统处于待测状态。随后主机发出激光发射指令EN,激光器向目标发射激光,同时ROIC中所有像素的时间-数字转换器(Time-to-digital Converter, TDC)开始计时。直到像素的探测器检测到反射的光子,TDC才停止计时。ROIC再将各个像素量化后的数据逐像素传出,实现图像处理与显示。
TDC直接将时间模拟信号转换为数字信号,同样需要具有高精度和高转换速度的性能。而利用时间放大、时间追赶等电路架构,传统独立TDC的时间分辨率已经可以达到1 ps以下[15-16]。但是,由于像素电路受到严格的面积和功耗限制(一般要求像素中心间距在50 μm以下),所以上述高精度TDC中常用的实现方法无法用于阵列TDC,导致阵列型TDC的精度难以提升。
在转换位数有限的条件下,TDC的量化精度和量程相互制约。对于宽动态范围的量化场合,传统的单模式TDC难以协调精度和量程之间的矛盾。而且单模式TDC如需改善分辨率、提高精度,就需要不断减小量化单位,导致时钟频率不断提高、功耗显著增大,因此,量化精度的提高也会受到系统功耗的限制。而由不同类型的单模式TDC共同组合(时空域变换)构成的分段式TDC,即有多种不同最低有效位(Least Significant Bit, LSB)作为量化单位的组合式TDC,能够以更低的代价高效实现多位量化,兼顾量程和精度,同时可以避免时钟频率和系统功耗的过度增加。
光子计时读出电路的主要性能指标为阵列规模、像素面积、时间分辨率、计时量程、帧频。其中时间分辨率是关键指标,阵列时间-数字转换电路受像素面积的严格限制,不能采用复杂电路结构,因此是一个较难实现的技术。同时时间分辨率与计时量程也是一个折中的关系,在像素面积和功耗的严格限制下,需要根据应用需求,选择到底是要看的远,还是要看的更清的问题。表1从工艺、像素规模、像元中心距、时间分辨率、计时量程、帧率和系统功耗对比了当前先进的光子计时读出电路的研究情况。
其次随着阵列规模的增大,TDC的功耗成为制约ROIC规模扩大的主要因素。瑞士洛桑理工学院是较早实现大面阵读出电路的研究机构之一[17],2008年,该机构提出了一种基于TDC共享架构的低功耗ROIC,阵列规模扩展至128×128,时间分辨率最高可达97 ps,系统架构如图5所示。在该阵列ROIC中仅有32个TDC模块,采用行扫描机制分时共享TDC,且一行中每四个像素为一组,一组共享一个TDC。由于采用TDC共享机制和逐行扫描方案,所以该系统仅需32个TDC即可实现128×128阵列的量化工作,极大地降低了系统功耗。又因为TDC位于像素阵列外部,面积较为宽裕,所以可以采用一种较为复杂的多段式TDC架构,最终系统的时间分辨率能够达到百皮秒以内。
表 1 光子计时读出电路的性能对比
Table 1. Performance comparison of photon timing readout circuit
Year 2018[18] 2020[19] 2020[20] 2018[21] 2019[22] Institution MIT Lincoln Laboratory University of Edinburgh Swiss Federal Institute of Technology Delft University of Technology Southeast University Technology 0.18 μm CMOS 40 nm CMOS 0.35 μm CMOS 0.18 μm CMOS 0.18 μm CMOS Pixel array 256×128 128×128 32×128 252×144 64×64 Pixel pitch 50 μm 40 μm×20 μm 40 μm 28.5 μm 50 μm TDC resolution 500 ps 100 ps 78 ps 48.8 ps 1000 ps TDC range - 23.3 ns 640 ns 333 ns 4000 ns Frame rate - 500 fps 20 fps 31.25 kfps 20 kfps Power - 185 mW - 2540 mW 490 mW TDC共享方案通过减少系统中TDC的个数来实现低功耗,同时TDC面积不受单个像素单元的限制,因此可以采用多段式TDC、时间放大等方法改善时间分辨率。TDC共享方案可以兼顾功耗与精度,但牺牲了成像分辨率和检测效率。共享架构导致使用同一个TDC的像素每帧只能探测一个返回光子,因此TDC共享技术主要适用于成像帧频要求不高、光子稀疏的特定应用场合。
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与基于TOF测量的ROIC不同,基于光子计数的ROIC在一个曝光时间内可以对光子到达信号进行多次检测。单位曝光时间内检测到的光子数量对应了不同的目标灰度信息,因此该类电路主要用于灰度成像。
光子计数读出电路的基本性能指标为阵列规模,像素面积、计数动态范围。像素面积越小,分辨率越高,成像质量越好。计数动态范围则是指一帧曝光内能检测到的光子个数的范围,动态范围受像素面积的限制。表2为光子计数读出电路的主要研究进展。
表 2 光子计数读出电路研究进展情况
Table 2. Research progress of photon counting readout circuit
Year 2015[23] 2020[24] 2022[25] 2019[26] 2021[27] Institution MIT Lincoln
LaboratoryOregon State
UniversityUniversity of
EdinburghTechnion-Israel
Institute of
TechnologySoutheast
UniversityTechnology 0.18 μm CMOS 0.18 μm CMOS 40 nm CMOS 0.18 μm CMOS 0.18 μm CMOS Pixel array 256×256 8×8 128×120 64×64 128×1 Pixel pitch 25 μm 80 μm 8 μm 25 μm 80 μm Dynamic range 42 dB 129 dB 126 dB - 60 dB 2015年,林肯实验室提出了一种基于硅盖革模式雪崩光电二极管(Geiger-mode Avalanche Photodiode, GM-APD)的256×256光子计数系统 [23]。该系统将一种硅GM-APD阵列与数字CMOS计数芯片混合集成,其单像素结构框图如图6所示,由APD探测器、APD接口电路、APD状态锁存器和7 bit计数器构成。像素中心距为25 μm,所有探测器的阳极被统一施加偏置电压,通过全局同步的脉冲信号来调控APD探测器的工作状态。
图 6 256×256光子计数系统的单像素结构框图
Figure 6. Single pixel structure block diagram of 256×256 photon counting system
由于每个像素接受到的光子个数不同,因此,每个像素都具有光子计数功能,可以对雪崩信号进行计数。理论上探测器在检测到光子并雪崩淬灭后,应立即复位以便准备下一次检测。但是,受探测器性能的限制,即连续工作会导致探测器的后脉冲发生率和暗计数率较高,所以还要加入探测器死区时间调节电路。死区时间的选取和确定需要综合多种因素,包括光子密度分布、光子探测率、精度、曝光时间、最大计数率等等,从而在不同光强条件下均能实现高精度的光子计数及数据读出。因此,在该类电路中,死区时间的调节方法是一个较为关键的技术。
2019年,东南大学提出一种光子时间自适应调节的读出电路结构,在电路系统中设置了判断电路,将一帧内检测到的光子个数与最佳死区时间存储于电路内,在实时检测光子过程中,对光子个数进行判断并与芯片内存储的死区时间进行对比,实时调节SPAD的死区时间,达到了最优的探测率。
光子计时是通过TDC对光子的飞行时间直接测量,在有限像素面积下,TDC精度和量程受到制约,且随着阵列规模扩大,TDC功耗会成倍增加。目前主流的解决方法是TDC共享,多个像素共享同一个TDC,节省了面积和功耗,但也带来了检测效率下降、成像分辨率下降的问题。光子计数是在像素中内置计数器,对探测到的光子计数。由于计数器不像TDC需要同时保证精度和量程,计数器所占的面积要远小于TDC,光子计数受到的像素面积的制约较小。但光子计数要求电路能够自恢复SPAD,这面临着后脉冲和暗计数问题,如何在保证探测效率的同时,最小化SPAD的后脉冲和暗计数是光子计数面临的关键问题。
Key technologies and development trends of SPAD array readout circuit (invited)
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摘要: 首先针对SPAD阵列读出电路的特点,将电路主要分成接口电路与信号处理电路两大部分,其次根据单光子雪崩光电探测器的阵列的不同应用场景,阐述了集成读出电路中核心电路模块设计的关键技术。分别从SPAD的接口电路设计、两种典型应用成像模式(光子计时、光子计数)中核心电路的设计方面,详细分析此类电路的关键技术以及国内外研究团队在此类电路的研究进展与存在的问题。最后根据目前国内外研究的进展情况,分析了SPAD阵列集成读出电路的发展趋势以及各类电路存在的设计重点与难点,为SPAD阵列读出电路的设计提供一些参考。Abstract:
Significance In recent years, the Single Photon Avalanche Diode(SPAD) with single-photon detection capability has been widely used in weak light detection fields such as laser radar, quantum communication, fluorescence spectrum analysis and so on because of its advantages of high sensitivity, fast response, strong anti-interference ability and small size. As a new nonlinear device, SPAD detector has complex manufacturing process. In addition, various applications of SPAD array need readout integrated circuits (ROIC) for detecting sensing signals to be matched with them to achieve the extraction and processing of SPAD detector avalanche signals. Various applications have increasingly high requirements for array size, detector signal extraction and processing capabilities. At the same time, the parasitic effect, power consumption, area and other problems caused by large-scale array are becoming more and more prominent, which seriously affects the imaging quality. The design of array-type SPAD readout circuit is facing great challenges. Progress The readout circuit of SPAD array is mainly composed of interface circuit and signal processing circuit. The interface circuit realizes the quenching and extraction of avalanche signal, and the switching between the cut-off and the state to be measured of SPAD. It is a dynamic bias circuit. With the expansion of the array scale, it is required to add SPAD anti-bias voltage adjustable circuit in the interface circuit, realize pixel-by-pixel or regionally adjustable bias of SPAD, and SPAD high-voltage breakdown protection circuit. At present, such technology is only used in small-scale, linear array and some applications, but still cannot be realized in the application of large area array. The main difficulty is that complex circuits cannot be used due to the limitation of pixel area. According to the application of SPAD, the signal processing circuit is divided into photon timing circuit and photon counting circuit. The photon timing circuit is used to measure the flight time of photons. In the circuit, the array-type time-to-digital conversion circuit (TDC) is used. Because the arrival time of each pixel is different, each pixel needs an independent TDC, and the circuit power consumption is very high. This is also one of the reasons that limit the scale expansion of SPAD array. A related research team has proposed a TDC sharing structure, such as the Lausanne Institute of Technology in Switzerland, which proposed a TDC sharing structure (Fig.3). At the same time, because the pixel area is not limited by sharing, multi-segment TDC can be used, and the time resolution of the circuit is less than 100 ps. Compared with the photon timing circuit, the structure of the photon counting circuit is relatively simple. It only needs to record the number of photons detected in a frame. The difficulty of this kind of circuit is to effectively adjust the dead time of the SPAD detector to achieve the best compromise between the detection rate and the dark count. Conclusions and Prospects With the demand for SPAD large arrays and the development of readout circuits, the following development trends have emerged in relevant readout circuits in recent years: on-chip data storage, multiple echo detection of returned photon events, and free detection mode. With the further development of the application requirements of SPAD array, the readout circuit will integrate more functions, further develop towards the integration of sensing, memory and computing, and finally truly realize single-chip imaging. -
表 1 光子计时读出电路的性能对比
Table 1. Performance comparison of photon timing readout circuit
Year 2018[18] 2020[19] 2020[20] 2018[21] 2019[22] Institution MIT Lincoln Laboratory University of Edinburgh Swiss Federal Institute of Technology Delft University of Technology Southeast University Technology 0.18 μm CMOS 40 nm CMOS 0.35 μm CMOS 0.18 μm CMOS 0.18 μm CMOS Pixel array 256×128 128×128 32×128 252×144 64×64 Pixel pitch 50 μm 40 μm×20 μm 40 μm 28.5 μm 50 μm TDC resolution 500 ps 100 ps 78 ps 48.8 ps 1000 ps TDC range - 23.3 ns 640 ns 333 ns 4000 ns Frame rate - 500 fps 20 fps 31.25 kfps 20 kfps Power - 185 mW - 2540 mW 490 mW 表 2 光子计数读出电路研究进展情况
Table 2. Research progress of photon counting readout circuit
Year 2015[23] 2020[24] 2022[25] 2019[26] 2021[27] Institution MIT Lincoln
LaboratoryOregon State
UniversityUniversity of
EdinburghTechnion-Israel
Institute of
TechnologySoutheast
UniversityTechnology 0.18 μm CMOS 0.18 μm CMOS 40 nm CMOS 0.18 μm CMOS 0.18 μm CMOS Pixel array 256×256 8×8 128×120 64×64 128×1 Pixel pitch 25 μm 80 μm 8 μm 25 μm 80 μm Dynamic range 42 dB 129 dB 126 dB - 60 dB -
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